One or more embodiments relate to an operating method used in a read or verification method of a nonvolatile memory device.
In recent years, there is an increasing demand for nonvolatile memory devices which can be electrically programmed and erased and do not need the refresh function of rewriting data at specific intervals.
The nonvolatile memory cell is an element enabling electrical program/erase operations, and is configured to perform the program and erase operations by changing its threshold voltage as electrons are migrated by a strong electric field applied to a thin oxide layer.
In such a nonvolatile memory device, a read operation and a verification operation are performed in a similar way. In the state in which a bit line coupled to a cell to be read is precharged to a logic high level, a read operation or a verification operation is performed by supplying the word line of the cell to be read with a reference voltage to and turning off the remaining memory cells. If the threshold voltage level of the memory cell is higher than the reference voltage, the corresponding memory cell is turned off, so the voltage level of the bit line remains intact. However, if the corresponding memory cell is turned on because the threshold voltage level of the memory cell is lower than the reference voltage, the voltage of the bit line is discharged through a common source line of a ground state. That is, whether or not the threshold voltage of the cell to be read is higher than the reference voltage can be determined based on a change in the voltage level of the bit line.
In accordance with the read operation or the verification operation, if the threshold voltage of a memory cell coupled to an unselected bit line, which belongs to memory cells to which selected read/verification reference voltages are applied, is higher than the reference voltage, the corresponding memory cell is turned off, so two channels with different electrical properties are formed on the basis of the corresponding memory cell. That is, the voltage of a channel formed in memory cells coupled to a variable voltage input terminal of a ground state maintains 0 V. However, a channel formed in memory cells coupled between the memory cell and a source select transistor of a turned-off state remains in a floating state. Accordingly, there is a probability that the threshold voltage of the memory cells may rise because of a voltage applied to the gates of the memory cells.
Since a high pass voltage is applied to the gates of the memory cells, charges moved by a strong electric field may move to the floating gates because of a channel hot carrier injection (CHEI) phenomenon. Consequently, there is a possibility that the threshold voltage of the corresponding cells may rise. In particular, there is a probability that this phenomenon may worsen when the memory cells are in an erase state. This phenomenon is called “disturbance occurring during a read or verification operation.”
Meanwhile, in the case where the verification method is applied to a multi-level cell program method, the following problems may occur. In the multi-level cell program method, the voltage level of a bit line is evaluated on the basis of two or more different reference voltages. This evaluation is sequentially performed. Accordingly, in the case where, after the bit line is precharged once, two or more steps of sequentially evaluating the voltage level of the bit line are performed, in the steps subsequent to the second evaluation step, the voltage level of the bit line may vary because of external factors, such as the leakage current occurring in the bit line. Accordingly, a cell may be read as being programmed with a voltage lower than an actual threshold voltage, or a cell may be read as being programmed with a voltage higher than an actual threshold voltage. In particular, in a verification operation, over-program or under-program may occur owing to the measurement results.